Abstract—this paper describes the DS-CDMA Transmitter
and Receiver for two users. This project has been
implemented on Spartan 3 FPGA by using Verilog HDL.
Five separate modules have been implemented for
the transmitter which were the Convolutional Encoder, the
Frequency Divider, the Block Interleaver, the Long PN
Code, and the Walsh Code. On the Receiver Side two new
modules have been added the Walsh Code, and the Viterbi
Decoder. ModelSim SE 5.7g has been used for simulation.
While ISE Webpack 10.1 Xilinx has been used for
synthesizing, mapping, and for downloading the modules
on FPGA. This DS-CDMA system contains data rates up
to 50 Mbps.

Keywords:

DS-CDMA, FPGA, transmitter, receiver

Full Text:

Credits:

Talha saeed
Department of Electrical Engineering
COMSATS Institute of Information Technology (CIIT)
Islamabad, Pakistan

Zubair iftikharDepartment of Electrical Engineering
COMSATS Institute of Information Technology (CIIT)
Islamabad, Pakistan

Muhammad shoaib
Department of Electrical Engineering
COMSATS Institute of Information Technology (CIIT)
Islamabad, Pakistan

Bushra Ghouri
Department of Physics
COMSATS Institute of Information Technology (CIIT)
Islamabad, Pakistan

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