Distributed Arithmetic based FIR Filter

Hassan Azwar

Abstract


Distributed Arithmetic (DA) technique is one of the technique used for implementation of FIR filter. This technique consist of Look Up Table (LUT), shift register and accumulator. Based on this technique multipliers in FIR filter are removed [1]. Multiplication is performed through shift and addition operations. The LUT can be subdivided into a number of LUT to reduce the size of the LUT for higher order filter. Each LUT operates on a different set of filter taps. Analysis on the performance of various filter orders with different address length are done using Xilinx synthesis tool. The proposed architecture provides less area compared with existing structure of FIR filter. Almost 1% resources of the FPGA (Spartan 6 XC6LX16-CS324) is used in designing the DA based FIR filter. Maximum
frequency that we can run our design at 220MHz frequency.


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